Описание
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Затрагиваемое ПО
Arm C1-ultra firmwareArm C1-ultraArm C1-premium firmwareArm C1-premiumArm Cortex-a710 firmwareArm Cortex-a710Arm Cortex-x2 firmwareArm Cortex-x2Arm Cortex-x3 firmwareArm Cortex-x3Arm Cortex-x4 firmwareArm Cortex-x4Arm Cortex-x925 firmwareArm Cortex-x925Arm Neoverse-v2 firmwareArm Neoverse-v2Arm Neoverse-v3 firmwareArm Neoverse-v3Arm Neoverse-v3ae firmwareArm Neoverse-v3aeArm Neoverse-n2 firmwareArm Neoverse-n2
CVSS
| Балл | 7.9 — высокая |
| Вектор | CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N |
Источники
https://developer.arm.com/documentation/111546https://graph.volerion.com/view?ID=CVE-2025-0647